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ET1150 | EtherCAT ASICNew

ET1150 | EtherCAT ASIC

ET1150 | EtherCAT ASIC

ET1150 | EtherCAT ASIC

ET1150 | EtherCAT ASIC

The EtherCAT SubDevice Controller ASIC ET1150 offers additional functions to those already included in the ET1100.

 

  • drop-in compatible with ET1100 (3.3 V designs)
  • single power supply option, integrated DC/DC
  • increased DPRAM: 15 kB
  • 16 FMMUs & 16 SyncManager
  • dual process data interface (PDI)
  • 4 x independent DC latch & sync signals
  • new PDIs: SPI-Master, Quad-SPI, Octal-SPI
  • up to 5x faster PDI compared to ET1100 (config-dependent)
  • OTP one-time programmable memory for device information, configuration, and application usage
  • up to 5x lower power consumption (config-dependent)
  • JTAG for ESC status, boundary scan test, and OTP programming
  • built-in RAM self-test (BIST)
  • supports gigabit & fiber-optic PHYs (100 Mbit/s mode)

 

Like all Beckhoff ESCs, the EtherCAT protocol is processed in the hardware, thus guaranteeing high performance and real-time capability, regardless of any downstream slave microcontrollers and the software implemented on them. The supply voltage is 3.3 V or 2.5 V; the core voltage of 1.1 V is generated by the integrated LDO or, newly, by the integrated DC/DC converter, or can alternatively be fed in directly. The ET1150 supports I/O voltages of 3.3 V/2.5 V/1.8 V in two sections for PDI signals and communication ports 0 and 1.

Product status:

product announcement | estimated market release 2nd quarter 2026

Product information

Technical dataET1150
Number of EtherCAT ports4 (max. 4 x MII/RGMII)
FMMUs16
SYNC manager16
DPRAM15 kB
Distributed clocksyes (64 bit)
max. 4 x sync signals
max. 4 x latch signals
Process data interfacesup to two process data interfaces
32 bit digital I/O
SPI slave (1/2/4/8 MISO/MOSI signals)
SPI master (1/2/4/8 MISO/MOSI signals)
8/16/32 bit µC (PDI1 only 8 bit µC)
HousingBGA128, 10 x 10 mm

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